1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a non-volatile semiconductor memory device capable of preventing fuse cells of a flash cell fuse circuit from being programmed by a static electric charges and a method of controlling the same.
2. Description of the Related Art
Semiconductor memory devices may be classified into volatile semiconductor memory devices and non-volatile semiconductor memory devices. In a volatile semiconductor memory device, data can be stored or erased by changing logic states of a bi-stable flip-flop, or data can be stored or erased by charging/discharging a capacitor. The data is maintained while power is supplied to the volatile semiconductor memory device, and the stored data is erased when the power is off.
In contrast, a non-volatile semiconductor memory device, such as a flash memory device, can preserve the stored data even when the power is off. Thus, the non-volatile semiconductor memory device is used for various devices, such as computers, mobile devices, and the like. The flash memory device is a non-volatile semiconductor memory device widely used as a secondary memory device for systems that need to be updated repeatedly. Generally, the flash memory device includes a flash cell fuse for generating a trim code.
FIG. 1 is a flow chart illustrating an early stage of a read operation in a conventional flash memory device. Referring to FIG. 1, a power-up operation is performed (step S1), a fuse cell voltage is sensed (step S2), a pumping operation of a read voltage is started (step S3), and a read operation is performed (step S4) in the early stage of the read operation.
FIG. 2 is a timing diagram illustrating an early stage of a read operation in a conventional flash memory device. Referring to FIG. 2, an external power supply voltage EVC increases to a power supply voltage VDD in a first time region REG1 where a power-up operation is performed. A power-up signal PUP is generated in the first time region REG1. In response to the power-up signal PUP, a fuse word-line enable signal FUSE_WL is activated, and a delayed power-up signal PUP_D is generated. A read enable signal VREAD_EN is activated in response to a falling edge of the delayed power-up signal PUP_D. A read voltage VREAD is generated in response to the read enable signal VREAD_EN.
Referring to FIG. 1 and FIG. 2, in the conventional flash memory device, the read voltage VREAD is generated after the fuse word-line enable signal FUSE_WL is activated. A voltage between a gate and a source of fuse cells that constitute the flash cell fuse circuit may be increased enough for programming the fuse cells in the first time region REG1 when static electric charges are input into the conventional flash memory device through input/output (I/O) pads. Therefore, it is desirable to have a flash memory device capable of preventing the fuse cells from being programmed by static electric charges.